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LTC2356-12/LTC2356-14 Serial 12-Bit/14-Bit, 3.5Msps Sampling ADCs with Shutdown Features
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Description
The LTC(R)2356-12/LTC2356-14 are 12-bit/14-bit, 3.5Msps serial ADCs with differential inputs. The devices draw only 5.5mA from a single 3.3V supply and come in a tiny 10-lead MSOP package. A Sleep shutdown feature further reduces power consumption to 13W. The combination of speed, low power and tiny package makes the LTC2356-12/LTC2356-14 suitable for high speed, portable applications. The 80dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. The devices convert -1.25V to 1.25V bipolar inputs differentially. The absolute voltage swing for AIN+ and AIN- extends from ground to the supply voltage. The serial interface sends out the conversion results during the 16 clock cycles following a CONV rising edge for compatibility with standard serial interfaces. If two additional clock cycles for acquisition time are allowed after the data stream in between conversions, the full sampling rate of 3.5Msps can be achieved with a 63MHz clock.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
3.5Msps Conversion Rate 74.1dB SINAD at 14-Bits, 71.1dB SINAD at 12-Bits Low Power Dissipation: 18mW 3.3V Single Supply Operation 2.5V Internal Bandgap Reference can be Overdriven 3-Wire SPI-Compatible Serial Interface Sleep (13W) Shutdown Mode Nap (4mW) Shutdown Mode 80dB Common Mode Rejection 1.25V Bipolar Input Range Tiny 10-Lead MSOP Package
applications
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Communications Data Acquisition Systems Uninterrupted Power Supplies Multiphase Motor Control Multiplexed Data Acquisition RFID
Block Diagram
10F 3.3V
THD, 2nd and 3rd vs Input Frequency for Differential Input Signals
VDD THREESTATE SERIAL OUTPUT PORT 14 14-BIT LATCH -50 -56 -62 8 SDO THD, 2nd, 3rd (dB) -68 -74 -80 -86 -92 9 SCK
2356 BD
LTC2356-14 AIN+ AIN- 1
7
+
S&H 14-BIT ADC
2
-
VREF 2.5V REFERENCE 6 11
THD 2nd 3rd
3 10F 4
10 TIMING LOGIC
CONV
GND 5
-98 -104 0.1 1 10 FREQUENCY (MHz) 100
2356 G02
EXPOSED PAD
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LTC2356-12/LTC2356-14 aBsolute maximum ratings
(Notes 1, 2)
pin conFiguration
TOP VIEW AIN+ AIN- VREF GND GND 1 2 3 4 5 10 9 8 7 6 CONV SCK SDO VDD GND 11
Supply Voltage (VDD) ..................................................4V Analog and VREF Input Voltages (Note 3) ....................................-0.3V to (VDD + 0.3V) Digital Input Voltages ................... - 0.3V to (VDD + 0.3V) Digital Output Voltage ...................- 0.3V to (VDD + 0.3V) Power Dissipation ...............................................100mW Operation Temperature Range LTC2356C-12/LTC2356C-14 .................... 0C to 70C LTC2356I-12/LTC2356I-14 ...................- 40C to 85C Storage Temperature Range .................. -65C to 150C Lead Temperature (Soldering, 10 sec)................... 300C
MSE PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125C, JA = 40C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
orDer inFormation
LEAD FREE FINISH LTC2356CMSE-12#PBF LTC2356IMSE-12#PBF LTC2356CMSE-14#PBF LTC2356IMSE-14#PBF TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP TEMPERATURE RANGE 0C to 70C -40C to 85C 0C to 70C -40C to 85C LTC2356CMSE-12#TRPBF LTCWN LTC2356IMSE-12#TRPBF LTCWN LTC2356CMSE-14#TRPBF LTCVF LTC2356IMSE-14#TRPBF LTCVF
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
converter characteristics
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Offset Error Gain Error Gain Tempco (Notes 4, 5, 18) (Notes 4, 18) (Note 4, 18) CONDITIONS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. With internal reference. VDD = 3.3V.
LTC2356-12 MIN
l l l l
LTC2356-14 MAX 2 10 40 MIN 14 -4 -30 -80 TYP 0.5 2 10 15 1 MAX 4 30 80 UNITS Bits LSB LSB LSB ppm/C ppm/C
TYP 0.25 1 5 15 1
12 -2 -10 -40
Internal Reference (Note 4) External Reference
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LTC2356-12/LTC2356-14 analog input
SYMBOL VIN VCM IIN CIN tACQ tAP tJITTER CMRR PARAMETER Analog Differential Input Range (Notes 3, 8, 9) Analog Common Mode + Differential Input Range (Note 10) Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio fIN = 1MHz, VIN = 0V to 3V fIN = 100MHz, VIN = 0V to 3V (Note 19) (Note 6)
l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. With internal reference. VDD = 3.3V.
CONDITIONS 3.1V VDD 3.6V
l
MIN
TYP -1.25 to 1.25 0 to VDD
MAX
UNITS V V
1 13 39 1 0.3 -60 -15
A pF ns ns ps dB dB
Dynamic accuracy
SYMBOL SINAD THD SFDR IMD PARAMETER Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Code-to-Code Transition Noise
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C with external reference = 2.55V. VDD = 3.3V. Single-ended AIN+ signal drive with AIN- = 1.5V DC. Differential signal drive with VCM = 1.5V at AIN+ and AIN-
LTC2356-12 CONDITIONS 100kHz Input Signal (Note 19) 1.4MHz Input Signal (Note 19) 100kHz First 5 Harmonics (Note 19) 1.4MHz First 5 Harmonics (Note 19) 100kHz Input Signal (Note 19) 1.4MHz Input Signal (Note 19) 0.625VP-P to 1.4MHz Summed with 0.625VP-P 1.56MHz into AIN+ and Inverted into AIN- VREF = 2.5V (Note 18)
l l
LTC2356-14 MAX MIN 70 -76 TYP 74.1 72.3 -86 -82 86 82 -82 1 50 5 -78 MAX UNITS dB dB dB dB dB dB dB LSBRMS MHz MHz
MIN 68
TYP 71.1 71.1 -86 -82 86 82 -82 0.25 50 5
Full Power Bandwidth VIN = 2.5VP-P, SDO = 11585LSBP-P (Note 15) Full Linear Bandwidth S/(N + D) 68dB
internal reFerence characteristics
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance VREF Settling Time External VREF Input Range VDD = 3.1V to 3.6V, VREF = 2.5V Load Current = 0.5mA CREF = 10F CONDITIONS IOUT = 0
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 3.3V.
MIN TYP 2.5 15 600 0.2 2 2.55 VDD MAX UNITS V ppm/C V/V ms V
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LTC2356-12/LTC2356-14 Digital inputs anD Digital outputs
SYMBOL VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage DOUT Hi-Z Output Capacitance DOUT Output Short-Circuit Source Current Output Short-Circuit Sink Current VOUT = 0V, VDD = 3.3V VOUT = VDD = 3.3V VDD = 3.3V, IOUT = -200A VDD = 3.1V, IOUT= 160A VDD = 3.1V, IOUT = 1.6mA VOUT = 0V to VDD
l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 3.3V.
CONDITIONS VDD = 3.6V VDD = 3.1V VIN = 0V to VDD
l l l
MIN 2.4
TYP
MAX 0.6 10
UNITS V V A pF V V V A pF mA mA
5 2.5 2.9 0.05 0.10 1 20 15 0.4 10
power requirements
SYMBOL VDD IDD PARAMETER Supply Voltage Supply Current
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 17)
CONDITIONS Active Mode Nap Mode Sleep Mode (LTC2356-12) Sleep Mode (LTC2356-14) Active Mode with SCK in Fixed State (Hi or Lo)
l l
MIN 3.1
TYP 3.3 5.5 1.1 4 4 18
MAX 3.6 8 1.5 15 12
UNITS V mA mA A A mW
PD
Power Dissipation
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LTC2356-12/LTC2356-14 timing characteristics
SYMBOL PARAMETER fSAMPLE(MAX) Maximum Sampling Rate per Channel (Conversion Rate) tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisiton Period) tSCK tCONV t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t12 Clock Period Conversion Time Minimum High or Low SCLK Pulse Width CONV to SCK Setup Time Nearest SCK Edge Before CONV Minimum High or Low CONV Pulse Width SCK to Sample Mode CONV to Hold Mode 16th SCK to CONV Interval (Affects Acquisition Period) Delay from SCK to Valid Data SCK to Hi-Z at SDO Previous SDO Bit Remains Valid After SCK VREF Settling Time After Sleep-to-Wake Transition (Note 16) (Note 6) (Note 6) (Notes 6, 10) (Note 6) (Note 6) (Note 6) (Notes 6, 11) (Notes 6, 7, 13) (Notes 6, 12) (Notes 6, 12) (Notes 6, 12) (Note 14) 2 2
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 3.3V.
CONDITIONS
l l l
MIN 3.5
TYP
MAX
UNITS MHz
286 15.872 16 2 3 0 4 4 1.2 45 8 6 18 10000
ns ns SCLK cycles ns ns ns ns ns ns ns ns ns ns ms
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: When these pins are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below GND or greater than VDD without latchup. Note 4: Offset and full-gain specifications are measured for a single-ended AIN+ input with AIN- grounded and using the internal 2.5V reference. Note 5: Integral linearity is tested with an external 2.55V reference and is defined as the deviation of a code from the straight line passing through the actual endpoints of a transfer curve. The deviation is measured from the center of quantization band. Note 6: Guaranteed by design, not subject to test. Note 7: Recommended operating conditions. Note 8: The analog input range is defined for the voltage difference between AIN+ and AIN-. Performance is specified with AIN- = 1.5V DC while driving AIN+. Note 9: The absolute voltage at AIN+ and AIN- must be within this range. Note 10: If less than 3ns is allowed, the output data will appear one clock cycle later. It is best for CONV to rise half a clock before SCK, when running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay is smaller (1ns) because the 2.2ns delay through the sample-and-hold is subtracted from the CONV to Hold mode delay. Note 12: The rising edge of SCK is guaranteed to catch the data coming out into a storage latch. Note 13: The time period for acquiring the input signal is started by the 16th rising clock and it is ended by the rising edge of convert. Note 14: The internal reference settles in 2ms after it wakes up from Sleep mode with one or more cycles at SCK and a 10F capacitive load. Note 15: The full power bandwidth is the frequency where the output code swing drops to 3dB with a 2.5VP-P input sine wave. Note 16: Maximum clock period guarantees analog performance during conversion. Output data can be read with an arbitrarily long clock. Note 17: VDD = 3.3V, fSAMPLE = 3.5Msps. Note 18: The LTC2356-14 is measured and specified with 14-bit resolution (1LSB = 152V) and the LTC2356-12 is measured and specified with 12-bit resolution (1LSB = 610V). Note 19: The sampling capacitor at each input accounts for 4.1pF of the input capacitance.
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LTC2356-12/LTC2356-14 typical perFormance characteristics
SINAD vs Input Frequency
77 74 71 68 SINAD (dB) 65 62 59 56 53 50 0.1 1 10 FREQUENCY (MHz) 100
2356 G01
TA = 25C, VDD = 3.3V (LTC2356-14)
THD, 2nd and 3rd vs Input Frequency
-50 -56 -62 THD, 2nd, 3rd (dB) -68 -74 -80 -86 -92 -98 -104 0.1 1 10 FREQUENCY (MHz) 100
2356 G02
THD 2nd 3rd
SFDR vs Input Frequency
92 86 80 SFDR (dB) SNR (dB) 74 68 62 56 50 0.1 1 10 FREQUENCY (MHz) 100
2356 G03
SNR vs Input Frequency
77 74 71 68 65 62 59 56 53 50 0.1 1 10 FREQUENCY (MHz) 100
2356 G04
100kHz Sine Wave 8192 Point FFT Plot
0 -10 -20 -30 MAGNITUDE (dB) -50 -60 -70 -80 -90 -100 -110 -120 MAGNITUDE (dB) -40 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
1.4MHz Sine Wave 8192 Point FFT Plot
0
250k 500k 750k 1M 1.25M 1.5M 1.75M FREQUENCY (Hz)
2356 G05
0
250k 500k 750k 1M 1.25M 1.5M 1.75M FREQUENCY (Hz)
2356 G06
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LTC2356-12/LTC2356-14 typical perFormance characteristics
TA = 25C, VDD = 3.3V (LTC2356-14)
Differential Linearity vs Output Code
1.0 0.8 DIFFERENTIAL LINEARITY (LSB) INTEGRAL LINEARITY (LSB) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 4096 12288 8192 OUTPUT CODE 16384
2356 G07
Integral Linearity vs Output Code
4 3 2 1 0 -1 -2 -3 -4 0 4096 8192 OUTPUT CODE
2356 G08
12288
16384
Differential and Integral Linearity vs Conversion Rate
4 3 2 LINEARITY (LSB) 1 0 -1 -2 -3 -4 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 CONVERSION RATE (Msps)
2356 G09
SINAD vs Conversion Rate, Input Frequency = 1.4MHz
75
74 MAX INL MAX DNL MIN DNL MIN INL SINAD (dB) 73
72 71
70 2.0 2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8 4.0
2356 G10
CONVERSION RATE (Msps)
12 6 0 AMPLITUDE (dB)
2.5VP-P Power Bandwidth
CMRR vs Frequency
0 -20 -40 CMRR (dB) -60 -80 -100 -120 100
-6 -12 -18 -24 -30 -36 1M 10M 100M FREQUENCY (Hz) 1G
2356 G11
1k
10k 100k 1M FREQUENCY (Hz)
10M
100M
2356 G12
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LTC2356-12/LTC2356-14 typical perFormance characteristics
PSRR vs Frequency
-25 -30 -35 -40 PSRR (dB) VREF (V) -45 -50 -55 -60 -65 -70 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M 2.4902 2.4900 2.4898 2.4896 2.4894 2.4892 2.4890
TA = 25C, VDD = 3.3V (LTC2356-12 and LTC2356-14)
Internal Reference Voltage vs Load Current
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (mA)
2356 G14
2356 G13
Internal Reference Voltage vs VDD
2.4902 2.4900 2.4898 VREF (V) 2.4896 2.4894 2.4892 2.4890 6 5.5 VDD SUPPLY CURRENT (mA) 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 2.6 2.8 3.0 3.2 VDD (V) 3.4 3.6
2356 G15
VDD Supply Current vs Conversion Rate
0
0
0.5
1
1.5
2
2.5
3
3.5
4
CONVERSION RATE (Mps)
2356 G16
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LTC2356-12/LTC2356-14 pin Functions
AIN+ (Pin 1): Noninverting Analog Input. AIN+ operates fully differentially with respect to AIN- with a -1.25V to 1.25V differential swing with respect to AIN- and a 0V to VDD common mode swing. AIN- (Pin 2): Inverting Analog Input. AIN- operates fully differentially with respect to AIN+ with a 1.25V to -1.25V differential swing with respect to AIN+ and a 0V to VDD common mode swing. VREF (Pin 3): 2.5V Internal Reference. Bypass to GND and to a solid analog ground plane with a 10F ceramic capacitor (or 10F tantalum in parallel with 0.1F ceramic). Can be overdriven by an external reference between 2.55V and VDD. GND (Pins 4, 5, 6, 11): Ground and Exposed Pad. These ground pins and the exposed pad must be tied directly to the solid ground plane under the part. Keep in mind that analog signal currents and digital output signal currents flow through these pins. VDD (Pin 7): 3.3V Positive Supply. This single power pin supplies 3.3V to the entire device. Bypass to GND and to a solid analog ground plane with a 10F ceramic capacitor (or 10F tantalum in parallel with 0.1F ceramic). Keep in mind that internal analog currents and digital output signal currents flow through this pin. Care should be taken to place the 0.1F bypass capacitor as close to Pins 6 and 7 as possible. SDO (Pin 8): Three-State Serial Data Output. Each set of output data words represents the difference between AIN+ and AIN- analog inputs at the start of the previous conversion. The output format is 2's complement. SCK (Pin 9): External Clock Input. Advances the conversion process and sequences the output data on the rising edge. Responds to TTL (3.3V) and 3.3V CMOS levels. One or more pulses wake from sleep. CONV (Pin 10): Convert Start. Holds the analog input signal and starts the conversion on the rising edge. Responds to TTL (3.3V) and 3.3V CMOS levels. Two CONV pulses with SCK in fixed high or fixed low state start Nap mode. Four or more CONV pulses with SCK in fixed high or fixed low state start Sleep mode.
Block Diagram
10F 3.3V 7
LTC2356-14 AIN+ AIN- 1
VDD THREESTATE SERIAL OUTPUT PORT 14 14-BIT LATCH
+
S&H 14-BIT ADC
8
SDO
2
-
VREF 2.5V REFERENCE 6 11
3 10F 4
10 TIMING LOGIC 9 EXPOSED PAD
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CONV
GND 5
SCK
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LTC2356-12/LTC2356-14 timing Diagram
LTC2356-12 Timing Diagram
t2 t3 17 SCK t4 CONV t6 INTERNAL S/H STATUS SAMPLE t8 SDO Hi-Z SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X* X* HOLD t8 SAMPLE t9 Hi-Z
2356 TD01
t1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 t5 16
t7 17 18 1
18
1
tACQ HOLD
14-BIT DATA WORD tCONV tTHROUGHPUT *BITS MARKED "X" AFTER D0 SHOULD BE IGNORED.
LTC2356-14 Timing Diagram
t2 t3 17 SCK t4 CONV t6 INTERNAL S/H STATUS SAMPLE t8 SDO Hi-Z SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 HOLD t8 SAMPLE t9 Hi-Z
2356 TD01b
t1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 t5 16
t7 17 18 1
18
1
tACQ HOLD
14-BIT DATA WORD tCONV tTHROUGHPUT
Nap Mode and Sleep Mode Waveforms
SCK
t1
CONV
t1
NAP
SLEEP
t12
VREF
NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS
2356 TD02
SCK to SDO Delay
SCK t10 SDO t8 VOH VOL SDO
2356 TD03
VIH
SCK t9
VIH
90% 10%
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0
LTC2356-12/LTC2356-14 applications inFormation
DRIVING THE ANALOG INPUT The differential analog inputs of the LTC2356-12/LTC2356-14 may be driven differentially or as a single-ended input (i.e., the AIN- input is set to VCM). Both differential analog inputs, AIN+ and AIN-, are sampled at the same instant. Any unwanted signal that is common to both inputs of each input pair will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sampleand-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC2356-12/LTC2356-14 inputs can be driven directly. As source impedance increases, so will acquisition time. For minimum acquisition time with high source impedance, a buffer amplifier must be used. The main requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 39ns for full throughput rate). Also keep in mind while choosing an input amplifier the amount of noise and harmonic distortion added by the amplifier. CHOOSING AN INPUT AMPLIFIER Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (<100) at the closed-loop bandwidth frequency. For example, if an amplifier is used with a gain of 1 and has a unity-gain bandwidth of 50MHz, then the output impedance at 50MHz must be less than 100. The second requirement is that the closed-loop bandwidth must be greater than 40MHz to ensure adequate small-signal settling for full throughput rate. If slower op amps are used, more time for settling can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC2356-12/ LTC2356-14 will depend on the application. Generally, applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC2356-12/LTC2356-14. (More detailed information is available in the Linear Technology Databooks and our website at www.linear.com.) LTC1566-1: Low Noise 2.3MHz Continuous Time LowPass Filter. LT(R)1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier. 2.7V to 15V supplies. Very high AVOL, 500V offset and 520ns settling to 0.5LSB for a 4V swing. THD and noise are -93dB to 40kHz and below 1LSB to 320kHz (AV = 1, 2VP-P into 1k, VS = 5V), making the part excellent for AC applications (to 1/3 Nyquist) where rail-to-rail performance is desired. Quad version is available as LT1631. LT1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifier. 2.7V to 15V supplies. Very high AVOL, 1.5mV offset and 400ns settling to 0.5LSB for a 4V swing. It is suitable for applications with a single 5V supply. THD and noise are -93dB to 40kHz and below 1LSB to 800kHz (AV = 1, 2VP-P into 1k, VS = 5V), making the part excellent for AC applications where rail-to-rail performance is desired. Quad version is available as LT1633. LT1813: Dual 100MHz 750V/s 3mA Voltage Feedback Amplifier. 5V to 5V supplies. Distortion is -86dB to 100kHz and -77dB to 1MHz with 5V supplies (2VP-P into 500). Excellent part for fast AC applications with 5V supplies. LT1801: 80MHz GBWP -75dBc at 500kHz, 2mA/Amplifier, , 8.5nV/Hz. LT1806/LT1807: 325MHz GBWP -80dBc Distortion at , 5MHz, Unity-Gain Stable, R-R In and Out, 10mA/Amplifier, 3.5nV/Hz. LT1810: 180MHz GBWP -90dBc Distortion at 5MHz, Unity, Gain Stable, R-R In and Out, 15mA/Amplifier, 16nV/Hz. LT1818/LT1819: 400MHz, 2500V/s,9mA, Single/Dual Voltage Mode Operational Amplifier. LT6200: 165MHz GBWP -85dBc Distortion at 1MHz, , Unity-Gain Stable, R-R In and Out, 15mA/Amplifier, 0.95nV/Hz. LT6203: 100MHz GBWP -80dBc Distortion at 1MHz, , Unity-Gain Stable, R-R In and Out, 3mA/Amplifier, 1.9nV/Hz. LT6600-10: Amplifier/Filter Differential In/Out with 10MHz Cutoff.
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LTC2356-12/LTC2356-14 applications inFormation
INPUT FILTERING AND SOURCE IMPEDANCE The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC2356-12/LTC2356-14 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 50MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 1 shows a 47pF capacitor from AIN+ to ground and a 51 source resistor to limit the input bandwidth to 47MHz. The 47pF capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling-glitch sensitive circuitry. High quality capacitors and resistors should be used since these components can add distortion. NPO and silvermica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. When high amplitude unwanted signals are close in frequency to the desired signal frequency, a multiple pole filter is required. High external source resistance, combined with the 13pF of input capacitance, will reduce the rated 50MHz bandwidth and increase acquisition time beyond 39ns.
51 47pF VCM 1.5V DC 2 1 AIN+
inverting input. The 1.25V range is also ideally suited for AC-coupled signals in single supply applications. Figure 2 shows how to AC couple signals in a single supply system without needing a mid-supply 1.5V external reference. The DC common mode level is supplied by the previous stage that is already bounded by the single supply voltage of the system. The common mode range of the inputs extend from ground to the supply voltage VDD. If the difference between the AIN+ and AIN- inputs exceeds 1.25V, the output code will stay fixed at zero and all ones and if this difference goes below -1.25V, the output code will stay fixed at one and all zeros.
C2 1F R2 1.6k R1 1.6k LTC2356-12/ LTC2356-14 AIN+ 2 AIN- 3 VREF 1
2356 F02
VIN
R3 51 C3 56pF
C1 C4 1F 10F
+
C1, C2: FILM TYPE C3: COG TYPE C4: CERAMIC BYPASS
Figure 2. AC Coupling of AC Signals with 1kHz Low Cutoff Frequency
INTERNAL REFERENCE The LTC2356-12/LTC2356-14 has an on-chip, temperature compensated, bandgap reference that is factory trimmed to 2.5V to obtain a bipolar 1.25V input span. The reference amplifier output VREF, (Pin 3) must be bypassed with a capacitor to ground. The reference amplifier is stable with capacitors of 1F or greater. For the best noise performance, a 10F ceramic or a 10F tantalum in parallel with a 0.1F ceramic is recommended. The VREF pin can be overdriven with an external reference as shown in
3.5V TO 18V
AIN- LTC2356-12/ LTC2356-14 3 VREF 10F 11 GND
2356 F01
Figure 1. RC Input Filter
INPUT RANGE The analog inputs of the LTC2356-12/LTC2356-14 may be driven fully differentially with a single supply. Each input may swing up to 2.5VP-P individually. When using the internal reference, the non-inverting input should never be more than 1.25V more positive or more negative than the
LT1790-3 10F
3V
3
VREF LTC2356-12/ LTC2356-14
11
GND
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Figure 3. Overdriving VREF Pin with an External Reference
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LTC2356-12/LTC2356-14 applications inFormation
Figure 3. The voltage of the external reference must be higher than the 2.5V output of the internal reference. The recommended range for an external reference is 2.55V to VDD. An external reference at 2.55V will see a DC quiescent load of 0.75mA and as much as 3mA during conversion. INPUT SPAN VERSUS REFERENCE VOLTAGE The differential input range has a bipolar VREF/2 voltage span that equals the difference between the voltage at the reference buffer output VREF at Pin 3, and the voltage at the ground (Exposed Pad Ground). The differential input range of the ADC is 1.25V when using the internal reference. The internal ADC is referenced to these two nodes. This relationship also holds true with an external reference. DIFFERENTIAL INPUTS The LTC2356-12/LTC2356-14 have a unique differential sample-and-hold circuit that measures input voltages from ground to VDD. The ADC will always convert the bipolar difference of AIN+ - AIN-, independent of the common mode voltage at the inputs. The common mode rejection holds up at extremely high frequencies, see Figure 4. The only requirement is that both inputs not go below ground or exceed VDD. Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are largely independent of the common mode voltage. However, the offset error will vary. The change in offset error is typically less than 0.1% of the common mode voltage.
0 -20 -40 CMRR (dB) -60 -80 -100 -120 100 R4 499 R3 499 -5V C4 1F VIN 1.25VP-P MAX C3 1F R1 51
Figure 5 shows the ideal input/output characteristics for the LTC2356-12/LTC2356-14. The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, FS - 1.5LSB). The output code is straight binary with 1LSB = 2.5V/16384 = 153V for the LTC2356-14, and 1LSB = 2.5V/4096 = 610V for the LTC2356-12. The LTC2356-14 has 1LSB RMS of random white noise. Figure 6a shows the LTC1819 converting a single ended input signal to differential input signals for optimum THD and SFDR performance as shown in the FFT plot (Figure 6b).
011...111 2'S COMPLEMENT OUTPUT CODE 011...110 011...101
100...010 100...001 100...000 -FS INPUT VOLTAGE (V)
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FS - 1LSB
Figure 5. LTC2356-12/LTC2356-14 Transfer Characteristic
5V
C5 0.1F
1k
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Figure 4. CMRR vs Frequency
Figure 6a. The LT1819 Driving the LTC2356-14 Differentially
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+
10k 100k 1M FREQUENCY (Hz)
10M
100M
+ -
-
U1 1/2 LT1819 C6 0.1F
1 C1 47pF TO 1000pF
AIN+
R5 1k 1.5VCM R6 1k R2 51
LTC2356-14
U2 1/2 LT1819
C2 47pF TO 1000pF
AIN-
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LTC2356-12/LTC2356-14 applications inFormation
0 -10 -20 MAGNITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 185k 371k 556k FREQUENCY (Hz) 741k
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VREF BYPASS 0805 SIZE
Figure 6b. LTC2356-12 6MHz Sine Wave 4096 Point FFT Plot with the LT1819 Driving the Inputs Differentially
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Board Layout and Bypassing Wire wrap boards are not recommended for high resolution and/or high speed A/D converters. To obtain the best performance from the LTC2356-12/LTC2356-14, a printed circuit board with ground plane is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track. If optimum phase match between the inputs is desired, the length of the two input wires should be kept matched. High quality tantalum and ceramic bypass capacitors should be used at the VDD and VREF pins as shown in the Block Diagram on the first page of this data sheet. For optimum performance, a 10F surface mount Tantalum capacitor with a 0.1F ceramic is recommended for the VDD and VREF pins. Alternatively, 10F ceramic chip capacitors such as Murata GRM219R60J106M may be used. The capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. Figure 7 shows the recommended system ground connections. All analog circuitry grounds should be terminated at the LTC2356-12/LTC2356-14 GND (Pins 4, 5, 6 and exposed pad). The ground return from the LTC235612/LTC2356-14 (Pins 4, 5, 6 and exposed pad) to the power supply should be low impedance for noise free operation. In applications where the ADC data outputs
OPTIONAL INPUT FILTERING
VDD BYPASS 0805 SIZE
Figure 7. Recommended Layout
and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a Wait state during conversion or by using three-state buffers to isolate the ADC data bus. POWER-DOWN MODES Upon power-up, the LTC2356-12/LTC2356-14 is initialized to the active state and is ready for conversion. The Nap and Sleep mode waveforms show the power-down modes for the LTC2356-12/LTC2356-14. The SCK and CONV inputs control the power-down modes (see Timing Diagrams). Two rising edges at CONV, without any intervening rising edges at SCK, put the LTC2356-12/LTC2356-14 in Nap mode and the power consumption drops from 18mW to 4mW. The internal reference remains powered in Nap mode. One or more rising edges at SCK wake up the LTC2356-12/LTC2356-14 very quickly, and CONV can start an accurate conversion within a clock cycle. Four rising edges at CONV, without any intervening rising edges at SCK, put the LTC2356-12/LTC2356-14 in Sleep mode and the power consumption drops from 18mW to 13W. One or more rising edges at SCK wake up the LTC2356-12/LTC2356-14 for operation. The internal reference (VREF ) takes 2ms to slew and settle with a 10F load.
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LTC2356-12/LTC2356-14 applications inFormation
Note that, using sleep mode more frequently than every 2ms, compromises the settled accuracy of the internal reference. Note that, for slower conversion rates, the Nap and Sleep modes can be used for substantial reductions in power consumption. DIGITAL INTERFACE The LTC2356-12/LTC2356-14 has a 3-wire SPI-compatible (Serial Protocol Interface) interface. The SCK and CONV inputs and SDO output implement this interface. The SCK and CONV inputs accept swings from 3.3V logic and are TTL compatible, if the logic swing does not exceed VDD. A detailed description of the three serial port signals follows. Conversion Start Input (CONV) The rising edge of CONV starts a conversion, but subsequent rising edges at CONV are ignored by the LTC2356-12/ LTC2356-14 until the following 16 SCK rising edges have occurred. It is necessary to have a minimum of 16 rising edges of the clock input SCK between rising edges of CONV. But to obtain maximum conversion speed (with a 63MHz SCK), it is necessary to allow two more clock periods between conversions to allow 39ns of acquisition time for the internal ADC sample-and-hold circuit. With 16 clock periods per conversion, the maximum conversion rate is limited to 3.5Msps to allow 39ns for acquisition time. In either case, the output data stream comes out within the first 16 clock periods to ensure compatibility with processor serial ports. The duty cycle of CONV can be arbitrarily chosen to be used as a frame sync signal for the processor serial port. A simple approach to generate CONV is to create a pulse that is one SCK wide to drive the LTC2356-12/LTC2356-14 and then buffer this signal with the appropriate number of inverters to ensure the correct delay driving the frame sync input of the processor serial port. It is good practice to drive the LTC2356-12/ LTC2356-14 CONV input first to avoid digital noise interference during the sample-to-hold transition triggered by CONV at the start of conversion. It is also good practice to keep the width of the low portion of the CONV signal greater than 15ns to avoid introducing glitches in the front end of the ADC just before the sample-and-hold goes into hold mode at the rising edge of CONV. Minimizing Jitter on the CONV Input In high speed applications where high amplitude sine waves above 100kHz are sampled, the CONV signal must have as little jitter as possible (10ps or less). The square wave output of a common crystal clock module usually meets this requirement . The challenge is to generate a CONV signal from this crystal clock without jitter corruption from other digital circuits in the system. A clock divider and any gates in the signal path from the crystal clock to the CONV input should not share the same integrated circuit with other parts of the system. As shown in Figure 8, the SCK and CONV inputs should be driven first, with digital buffers used to drive the serial port interface. Also note that the master clock in the DSP may already be corrupted with jitter, even if it comes directly from the DSP crystal. Another problem with high speed processor clocks is that they often use a low cost, low speed crystal (i.e., 10MHz) to generate a fast, but jittery, phase-locked-loop system clock (i.e., 40MHz). The jitter in these PLL-generated high speed clocks can be several nanoseconds. Note that if you choose to use the frame sync signal generated by the DSP port, this signal will have the same jitter of the DSP's master clock. The Typical Application Figure on page 16 shows a circuit for level-shifting and squaring the output from an RF signal generator or other low-jitter source. A single D-type flip flop is used to generate the CONV signal to the LTC2356-12/LTC2356-14. Re-timing the master clock signal eliminates clock jitter introduced by the controlling device (DSP FPGA, etc.) Both the inverter and flip flop must , be treated as analog components and should be powered from a clean analog supply. Serial Clock Input (SCK) The rising edge of SCK advances the conversion process and also udpates each bit in the SDO data stream. After CONV rises, the third rising edge of SCK starts clocking out the 12/14 data bits with the MSB sent first. A simple approach is to generate SCK to drive the LTC2356-12/ LTC2356-14 first and then buffer this signal with the appropriate number of inverters to drive the serial clock input of the processor serial port. Use the falling edge of the clock to latch data from the Serial Data Output (SDO)
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LTC2356-12/LTC2356-14 applications inFormation
into your processor serial port. The 14-bit serial data will be received right justified, in a 16-bit word with 16 or more clocks per frame sync. It is good practice to drive the LTC2356-12/LTC2356-14 SCK input first to avoid digital noise interference during the internal bit comparison decision by the internal high speed comparator. Unlike the CONV input, the SCK input is not sensitive to jitter because the input signal is already sampled and held constant. Serial Data Output (SDO) Upon power-up, the SDO output is automatically reset to the high impedance state. The SDO output remains in high impedance until a new conversion is started. SDO sends out 12/14 bits in 2's complement format in the output data stream beginning at the third rising edge of SCK after the rising edge of CONV. SDO is always in high impedance mode when it is not sending out data bits. Please note the delay specification from SCK to a valid SDO. SDO is always guaranteed to be valid by the next rising edge of SCK. The 16-bit output data stream is compatible with the 16-bit or 32-bit serial port of most processors. Loading on the SDO line must be minimized. SDO can directly drive most fast CMOS logic inputs directly. However, the general purpose I/O pins on many programmable logic devices (FPGAs, CPLDs) and DSPs have excessive capacitance. In these cases, a 100 resistor in series with SDO can isolate the input capacitance of the receiving device. If the receiving device has more than 10pF of input capacitance or is located far from the LTC235612/LTC2356-14, an NC7SVU04P5X inverter can be used to provide more drive.
package Description
MSE Package 10-Lead Plastic MSOP Exposed Die Pad ,
(Reference LTC DWG # 05-08-1664 Rev C)
3.00 0.102 (.118 .004) (NOTE 3) BOTTOM VIEW OF EXPOSED PAD OPTION 1 2.06 0.102 (.081 .004) 1.83 0.102 (.072 .004) 0.05 REF DETAIL "B" CORNER TAIL IS PART OF DETAIL "B" THE LEADFRAME FEATURE. FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 0.29 REF
10 9 8 7 6
0.497 0.076 (.0196 .003) REF
4.90 0.152 (.193 .006) 0.254 (.010)
GAUGE PLANE DETAIL "A" 0 - 6 TYP
3.00 0.102 (.118 .004) (NOTE 4)
12345 0.53 0.152 (.021 .006)
DETAIL "A"
10 0.86 (.034) REF
1.10 (.043) MAX
2.794 (.110
0.102 .004)
0.889 (.035
0.127 .005)
0.18 (.007)
SEATING PLANE
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.17 - 0.27 (.007 - .011) TYP
0.50 (.0197) BSC
0.1016 (.004
0.0508 .002)
MSOP (MSE) 0908 REV C
5.23 (.206) MIN
2.083 (.082
0.102 3.20 - 3.45 .004) (.126 - .136)
0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT
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LTC2356-12/LTC2356-14 revision history
REV A DATE 01/10 DESCRIPTION Revise Values in Pin Configuration Section PAGE NUMBER 2
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC2356-12/LTC2356-14 typical application
Low-Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level Shifting Circuit and Re-Timing Flip-Flop
VCC 0.1F 1k NC7SVU04P5X MASTER CLOCK VCC 50 1k
PRE D Q Q CLR NL17SZ74
CONV
CONTROL LOGIC (FPGA, CPLD, DSP, ETC.)
CONVERT ENABLE CONV LTC2356 SCK SDO
NC7SVU04P5X 100
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relateD parts
PART NUMBER ADCs LTC1402 LTC1403/LTC1403A LTC1403-1/LTC1403A-1 LTC1405 LTC1407/LTC1407A LTC1407-1/LTC1407A-1 LTC1411 LTC1412 LCT1414 LTC1420 LTC1604 LTC1608 LTC1609 LTC1864/LTC1865 LTC2355-12/LTC2355-14 DACs LTC1666/LTC1667/LTC1668 LTC1592 References LT1790-2.5 LT1461-2.5 LT1460-2.5 Micropower Series Reference in SOT-23 Precision Voltage Reference Micropower Series Voltage Reference 0.05% Initial Accuracy, 10ppm Drift 0.04% Initial Accuracy, 3ppm Drift 0.1% Initial Accuracy, 10ppm Drift
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DESCRIPTION 12-Bit, 2.2Msps Serial ADC 12-/14-Bit, 2.8Msps Serial ADC 12-/14-Bit, 2.8Msps Serial ADC 12-Bit, 5Msps Parallel ADC 12-/14-Bit, 3Msps Simultaneous Sampling ADC 12-/14-Bit, 3Msps Simultaneous Sampling ADC 14-Bit, 2.5Msps Parallel ADC 12-Bit, 3Msps Parallel ADC 14-Bit, 2.2Msps Parallel ADC 12-Bit, 10Msps Parallel ADC 16-Bit, 333ksps Parallel ADC 16-Bit, 500ksps Parallel ADC 16-Bit, 250ksps Serial ADC 16-Bit, 250ksps Serial ADCs 12-/14-Bit, 3.5Msps Serial ADC 12-/14-/16-Bit, 50Msps DACs 16-Bit, Serial SoftSpanTM IOUT DAC
COMMENTS 5V or 5V Supply, 4.096V or 2.5V Span 3V, 15mW, Unipolar Inputs, MSOP Package 3V, 15mW, Bipolar Inputs, MSOP Package 5V, Selectable Spans, 115mW 3V, 2-Channel Differential, Unipolar Inputs, 14mW, MSOP Package 3V, 2-Channel Differential, Bipolar Inputs, 14mW, MSOP Package 5V, Selectable Spans, 80dB SINAD 5V Supply, 2.5V Span, 72dB SINAD 5V Supply, 2.5V Span, 78dB SINAD 5V, Selectable Spans, 72dB SINAD 5V Supply, 2.5V Span, 90dB SINAD 5V Supply, 2.5V Span, 90dB SINAD 5V, Configurable Bipolar/Unipolar Inputs 5V Supply, 1 and 2 Channel, 4.3mW, MSOP Package 3.3V 14mW, 0V to 2.5V Span, MSOP Package 87dB SFDR, 20ns Settling Time 1LSB INL/DNL, Software Selectable Spans
SoftSpan is a trademark of Linear Technology Corporation.
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
LT 0110 REV A * PRINTED IN USA
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2006

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